The present invention relates to a smooth sequence generator that is capable of dividing a uniform pulse sequence by virtually any proper, predetermined, rational fraction.
Apparatus has been proposed heretofore for dividing a uniform pulse sequence by an arbitrarily variable value-- see, for example, the patent to E. T. Colton, U.S. Pat. No. 3,297,953, issued Jan. 10, 1967. The cited patent is typical of the genre and includes a rate multiplier, a voltage controlled oscillator VCO (in addition to the reference source oscillator) and a phase-locked loop in which the VCO is coupled. Besides the complexity of this prior art divider circuitry, it has been found to be limited in the division ratio that can be achieved. Again by way of example, the circuit of the cited Colton patent provides an output frequency (i.e., output pulse rate) which is quite restricted in its (division) range vis-a-vis the reference frequency or reference pulse sequence (see the Colton patent, column 2, lines 21-26).
It is accordingly a primary object of the present invention to provide apparatus that is capable of dividing a uniform pulse sequence by virtually any predetermined, proper rational fraction.
The necessity increasingly arises in digital systems to generate an external pulse rate whose frequency is related to a reference clock frequency by some (unusual) proper rational fraction while still maintaining synchronism with the reference clock source. In many such cases, it is a requirement that pulses of the generated frequency be as uniformly spaced as possible within the constraint of synchronism. Such pulse sequences are called "smooth" in contrast with uniform pulse sequences in which each pulse is separated from its predecessor by a fixed interval. The smooth sequences possess a number of interesting properties in their structure; these properties are treated in the article "Smooth Pulse Sequences" by A. J. Lincoln et al, Proceedings of the Third Annual Princeton Conference on Information Sciences and Systems, 1969, pp. 350-354.
A technique commonly used for forming these synchronous frequency multiples uses the "rate multipler" and involves detecting the zero-to-one transitions of the stages of a binary counter chain. The rate multiplier technique, although often capable of forming relatively smooth sequences, does not form a true smooth sequence, as has been noted in the above-cited article by A. J. Lincoln et al.
It is a further object of the invention to achieve a smooth pulse sequence with a minimal of timing uncertainty.
A still further object of the invention is to provide a circuit which implements the smooth pulse sequence function in an expeditious and economical manner.